The TTL control I/O option for the SIS3316 is finally available.
It conists of two piggy cards that can be installed on new units or retrofitted on existing boards in the factory or by skilled electronics workshop personnel.
The outputs can drive about 40 mA or loads from 60 Ω on. The inputs have an impedance of 50 Ω or high impedance (given the termination jumper setting like in the NIM case).
SIS3316 TTL control I/O piggies
Thanks to Mark Rivers from the University of Chicago for proposing the incorporation of LNE/CIP delay, stretcher and invert functionality into the SIS3820 Multi Purpose Scaler firmware to facilitate the use of the LNE/CIP output to interface to external hardware. The implementation is available from firmware 0x0111 onwards. We’d like to thank Mark for the integration into the SIS3820 EPICS GUI and for testing the new functionality. A screenshot of the GUI is shown below.
SIS3820 EPICS GUI (Courtesy Mark Rivers, APS)
The firmware can be downloaded from www.struck.de/sis3820.htm
In operation mode 0 you have the effect on the LNE signal as illustrated below.
SIS3820 LNE Stretcher
In operation mode 2 you have the effect on the CIP signal as illustrated below.
SIS3820 CIP Stretcher
Issue: Installation of SIS1100 driver in a new work station with CENTOS7 results in error message upon compilation: make -C /lib/modules/3.10.0-123.8.1.el7.x86_64/build SUBDIRS=/home/dacq/SIS1100/sis1100-2.13-9/dev/pci modules make: *** /lib/modules/3.10.0-123.8.1.el7.x86_64/build: No such file or directory. Stop. make: *** [driver] Error 2 Solution: Installation of the kernel-devel package
MLVDS Input/Output Control register 0x12 below release 0x1007 has a copy&paste bug in the top level VHDL code, which is affecting triggering of MLVDS input 7.
The bug is fixed in macro and synthesized versions from 0x1007 on.
Thanks to ESS/COSYLAB for bringing the bug to our attention and assistance in tracking it down.
Find the section below in case you would like to fix it in your code, which is based on our macro.
if rising_edge(sys_ad9510_no1_bufg_clk) then —
external_ored_trigger_signal <=
(ext_trigger_harlink_rising_pulse(1) and addr_0x13_reg_q(8) and not addr_0x13_reg_q(12) )
or (ext_trigger_harlink_falling_pulse(1) and addr_0x13_reg_q(8) and addr_0x13_reg_q(12) )
or (ext_trigger_harlink_rising_pulse(2) and addr_0x13_reg_q(9) and not addr_0x13_reg_q(13) )
or (ext_trigger_harlink_falling_pulse(2) and addr_0x13_reg_q(9) and addr_0x13_reg_q(13) )
or (ext_trigger_harlink_rising_pulse(3) and addr_0x13_reg_q(10) and not addr_0x13_reg_q(14) )
or (ext_trigger_harlink_falling_pulse(3) and addr_0x13_reg_q(10) and addr_0x13_reg_q(14) )
or (ext_trigger_harlink_rising_pulse(4) and addr_0x13_reg_q(11) and not addr_0x13_reg_q(15) )
or (ext_trigger_harlink_falling_pulse(4) and addr_0x13_reg_q(11) and addr_0x13_reg_q(15) )
or (ext_trigger_mlvds_rising_pulse(0) and addr_0x12_reg_q(8) and not addr_0x12_reg_q(0) )
or (ext_trigger_mlvds_falling_pulse(0) and addr_0x12_reg_q(8) and addr_0x12_reg_q(0) )
or (ext_trigger_mlvds_rising_pulse(1) and addr_0x12_reg_q(9) and not addr_0x12_reg_q(1) )
or (ext_trigger_mlvds_falling_pulse(1) and addr_0x12_reg_q(9) and addr_0x12_reg_q(1) )
or (ext_trigger_mlvds_rising_pulse(2) and addr_0x12_reg_q(10) and not addr_0x12_reg_q(2) )
or (ext_trigger_mlvds_falling_pulse(2) and addr_0x12_reg_q(10) and addr_0x12_reg_q(2) )
or (ext_trigger_mlvds_rising_pulse(3) and addr_0x12_reg_q(11) and not addr_0x12_reg_q(3) )
or (ext_trigger_mlvds_falling_pulse(3) and addr_0x12_reg_q(11) and addr_0x12_reg_q(3) )
or (ext_trigger_mlvds_rising_pulse(4) and addr_0x12_reg_q(12) and not addr_0x12_reg_q(4) )
or (ext_trigger_mlvds_falling_pulse(4) and addr_0x12_reg_q(12) and addr_0x12_reg_q(4) )
or (ext_trigger_mlvds_rising_pulse(5) and addr_0x12_reg_q(13) and not addr_0x12_reg_q(5) )
or (ext_trigger_mlvds_falling_pulse(5) and addr_0x12_reg_q(13) and addr_0x12_reg_q(5) )
or (ext_trigger_mlvds_rising_pulse(6) and addr_0x12_reg_q(14) and not addr_0x12_reg_q(6) )
or (ext_trigger_mlvds_falling_pulse(6) and addr_0x12_reg_q(14) and addr_0x12_reg_q(6) )
— or (ext_trigger_mlvds_rising_pulse(7) and addr_0x12_reg_q(14) and not addr_0x12_reg_q(7) )
— or (ext_trigger_mlvds_falling_pulse(7) and addr_0x12_reg_q(14) and addr_0x12_reg_q(7) ) ;
or (ext_trigger_mlvds_rising_pulse(7) and addr_0x12_reg_q(15) and not addr_0x12_reg_q(7) ) — mod. 22.08.2014
or (ext_trigger_mlvds_falling_pulse(7) and addr_0x12_reg_q(15) and addr_0x12_reg_q(7) ) ; — mod. 22.08.2014
end if;
Custom firmware was developed for the 16 channel SIS3316 250 MSPS 14-bit digitizer for a n/Gamma separation with firmware TOF (time of flight) histogramming capability. The user can configure the gates to be histogrammed. Both readout over VME and Ethernet SFP (e.g. for the SIS3316 Desktop System) are supported.
The implemented FPGA firmware of the has the following features:
In the screenshot below you can see the n/Gamma separation for particles from a Cf-252 source (with uniform TOF distribution in that case of course).
The combination of the SIS8300-L digitizer AMC and the DWC8VM1 Rear Transition Module (RTM) can be used as single cavity Low Level Radio Frequency (LLRF) controls solution for cavities with frequencies ranging from 700 MHz to 4 GHz. A first batch of 10 DWC8VM1 modules with different frequencies was build under license of DESY and shipped in March of 2014.
SIS8300-L/DWC8VM1 combination
The DWC8VM1 has 8 downconverter channels, 2 auxiliary analog input channels and one vectormodulator channel. After the analog to digital conversion of the intermediate frequency (IF) you can handle the signal processing in the Virtex 6 of the SIS8300-L digitizer board and control the vectormodulator channel with the dual digital to analog converter. The analog signals in between of the DWC8VM1 and SIS8300-L are routed over the Zone 3 connector.
The option to average over 4, 8, 16, 32, 64, 128 and 256 samples for slower speed sampling at higher resolution was added to the SIS3316 firmware.
Peak and charge sensing ADC functionality with external gate was added to the SIS3316 firmware (limited to the 250 MSPS version for the time being).
The current MMC code for the SIS8300 V2 and SIS8300-L MTCA.4 digitizers is available on the SIS8300 firmware page now.
More information on software support and performance will be put online shortly.
