SIS8300 Firmware revision page
SIS8300 V1 Generic Firmware Revision Table
| Design Name |
Major Revision # |
Minor Revision # |
Description |
MCS File |
| SIS8300 20.10.10 |
01 |
03 |
First official release |
V0103 |
| SIS8300 V1 Firmware Revision Table |
SIS8300 V2 Generic Firmware Revision Table
| Design Name |
Major Revision # |
Minor Revision # |
Description |
MCS File |
| SIS8300 |
0x11 |
0x02 |
Current release |
SIS8300V2 V1102 |
| SIS8300 |
0x14 |
0x00 |
New release w. histogramming memory controller for Virtex 5 SX |
SIS8300V2 SX V1400 |
| SIS8300 V2 Firmware Revision Table |
Note: The connection between the Serial PROM and the FPGA on the SIS8300 uses 8-bit parallel mode.
You will want to check the 'Parallel Load' box in Impact when specifying the programming properties for the PROM.
