The SIS1100/SIS3100 PCI/cPCI to VME interface card combination was developed to meet the requirements of demanding VME data acquisition systems. The link is optimized for low latency high speed readout. Interaction with external logic is possible through optional input/output connectors on the VME side (SIS3100) of the link. The actual VME transactions are handled by a sequencer. The sequencer can execute VME cycles under PC program control or under control of the optional Digital Signal Processor (DSP).
The flexible FPGA based design allows for the implementation of the traditional VME cycles as well as more recent extensions to the standard, like 2eVME e.g.
VME sequencer
Mapping table with 64 entries
VME master A16/A24/A32/A40 D8/D16/D32/BLT32/MBLT64/2eVME
VME slave A32/D32/BLT32/MBLT64
Block transfer address auto increment on/off (for FIFO reads)
System controller function (can be disabled by jumper)
up to 450 m link distance (up to 20 km with long distance option)
EMC front panel
in field JTAG firmware upgrade capability
|
LED's |
|
| A (access/slave) | M (master) |
| P (power) | S (sequencer) |
| R (ready) | L (link up) |
| LU (link data up) | LD (link data down) |
| U (user) | DU (dsp user) |
| Environment |
Performance |
|
| LINUX | BLT32 | 25 MBytes/s |
| MBLT64 | 50 MBytes/s | |
| 2eVME | >80 MBytes/s(*) | |
| Readout from SDRAM | 80 MBytes/s | |
| DSP VME single cycle | 600 ns/cycle | |
| measured with CI80 memory as VME slave | ||
| (*) measured with SIS3300 FADC as VME slave | ||
| Win2K/NI CVI | D32 | 5 µs/longword |
| mapped D32 read access | 3 µs/longword | |
| pipelined D32 write access | 700ns/longword | |
| MBLT64 read | 40 MBytes/s | |
upper trace: DS1, lower trace: DTACK
SIS9200 DSP piggy pack as histogrammer
64/128/256/512 MB slave/histogramming memory
4 flat cable inputs/4 flat cable outputs (ECL or high impedance TTL)
3 LEMO inputs/3 LEMO outputs (50 Ohm TTL or NIM level)
LEMO reset input (50 Ohm TTL or NIM level)
LEMO reset output (50 Ohm TTL or NIM level)
Monomode link medium (up to 5, 10 or 20 km link distance)
Deep transfer FIFOs
The PCI (SIS1100) side consists of two printed circuit boards. The first board is a CMC carrier board (SIS1100-CMC or SIS1100-cCMC) with a PLX 9054 PCI master bridge chip a FPGA and glue logic, like boot circuitry, the second card is the CMC optical link mezaninne card (SIS1100-OPT).
Link part as identical copy of VME side
|
LED's on SIS1100-OPT |
|
| A (access) | L (link up) |
| LU (link data up) | LD (link data down) |
| U (user) | spare |
Option: 2 LEMO TTL in and 2 LEMO TTL (50 Ohm) outputs
LINUX driver (Kernel 2.4.4 or higher required)
Multiple interface NT/Win2K/Windows XP driver/API
spec support
KMAX support
NI CVI/Labview support
IDL support (for SIS3300 digitizer)
BSD driver
Find below the front panel designs of the standard module (left hand side) and the design with front panel I/O option (right hand side)
The link between the PCI and the VME side is based on an optical GBit connection, small form factor link media are used for optimum space/performance ratio and electrical decoupling of the two sides. Find below a photograph of a link medium with attached fiber.
The optional DSP can be used to execute predefined command lists with minimum overhead. Conditional list execution allows for the implementation of different event types. Trigger/deadtime handling is straightforward, as the DSP can interact with the different inputs and outputs. Find below a sequencer list execution example for two event types and possible slow control execution.
More complex sequencer lists (as shown below) are possible under control of the optional DSP.
The development of the SIS PCI-VME interface is a collaborative effort of the ZEL department of the research center Juelich and SIS GmbH.