SIS8300 µTCA for Physics Digitizer

10 Channel 125 MS/s 16-bit With Fast Feedback DACs

Development in co-operation with DESY under ZIM Förderkennzeichen 2460101MS9

The SIS8300 is a MTCA.4 (µTCA for Physics) digitizer card. High speed readout is implemented via a Virtex 5 FPGA based four lane PCI Express lane implementation.

Rear Transition Modules (RTMs) for different applications have been developed by different institutes and companies.

An overview can be found in the PDF of the 2011 Valencia NSS xTCA Workshop also.

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SIS8300 photograph

Central Design Parameters

  • MTCA.4 (µTCA for Physics Implementation)
  • 4 lane PCI Express Connectivity
  • 10 Channels 125 MS/s 16-bit ADC
  • 10 MS/s to 125 MS/s Per Channel Sampling Speed
  • AC and DC Input Stage
  • Internal, Front Panel, RTM and Backplane Clock Sources
  • Two 16-bit DACs for Fast Feedback Implementation
  • High Precision Clock Distribution Circuitry
  • Programmable Delay of Dual Channel Digitizer Groups
  • Gigabit Link Port Implemenation to Backplane
  • Twin SFP Card Cage for High Speed System Interconnects
  • Virtex 5 FPGA
  • 32 MSample Memory per Channel
  • In Field Firmware Upgrade Support
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    Ordering Options
    Part Number Xilinx FPGA Memory
    04075 XC5VLX50T-3FFG1136C 4 x 1 GBit
    04364 XC5VSX50T-3FFG1136C 4 x 2 GBit
    05176 XC5VLX85T-1/3FFG1136C 4 x 2 GBit
    tbd XC5VLX110T-1/3FFG1136C 5 x 2 GBit
    SIS8300 Ordering Options
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    Available RTMs for the SIS8300 Digitizer
    Name Source Description
    SIS8900 Struck Single Ended Input Card
    RTM7201 HYTEC 4-channel signal modulator
    DWC8300 Struck Downconverter
    BPM DESY Interleaved sampling for BPM readout
    APD DESY Dual channel signal stretcher
    Fast ADC RTM SLAC LLRF ADC Frontend
    Available RTMs for SIS8300
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    Block Diagram of SIS8300 With Downconverter Rear Transition Module

    SIS8300 block diagramm with RTM vertical bar