>SIS330x Firmware revision table

SIS3300

Design Name Major Revision # Minor Revision # Description MCS Files
SIS3300V_070501 01 01 Initial Release V1 boards -
SIS3300V_301001 01 02 V2 boards -
SIS3300V_180102 01 03 Boot logic change -
SIS3300V_240502 03 01 Gate mode/Averaging/2eVME Bug in 2nd bank trigger bit generation!!!
SIS3300V_080602 03 02 bug fix (see above) obsolete
SIS3300V_260802 03 04 external clock bug fix obsolete
SIS3300V_311005 03 07 "Disable Bit" for time stamp clear sis3300v307.zip
SIS3300V_210104 10 02 Amanda design
non standard!!! 		sis3300amanda.zip
SIS3300V_310511 11 05 Greta design
non standard!!! 		sis3300v1105.zip

SIS3301

Design Name Major Revision # Minor Revision # Description MCS Files
SIS3301V_040102 02 02 Initial Release -
SIS3301V_240502 03 01 Gate mode/Averaging/2eVME Bug in 2nd bank trigger bit generation!!!
SIS3301V_080602 03 03 bug fix (see above) obsolete, use 0304
SIS3301V_260802 03 04 external clock bug fix obsolete
SIS3301V_221002 03 05 one wire Id. support use 0306
SIS3301V_110804 03 06 delay locked loop for external clock sis3301v306.zip
SIS3301V_041105 03 07 "Disable Bit" for time stamp clear
no one wire Id. support		 sis3301v307.zip
SIS3301V_060607 03 08 Page size map select bit
no one wire Id. support		 sis3301v308.zip
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JTAG firmware upgrade procedure

The firmware of the SIS3300 and SIS3301 can be ugraded with a XILINX JTAG programmer (XILINX part number HW-PC4 or HW-JTAG-PC e.g.) through the serial port of a Windows PC. Download PDF firmware upgrade instructions

With ISE12 you will have to download the XC18V04 configuration PROM BSDL models from the Xilinx web site and copy them to XILINX/12.2/ISE_DS/xc18v00/data (for ISE12.2. e.g) after backup of the existing *.bsd files.

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Known Bugs

The Trigger LED is not working on all SIS3300 and SIS3301 designs up to 03 04.