!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 4.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd"> SIS3820 firmware revision

SIS3820 Firmware revision table

SIS3820 Multi Purpose Counter
Design Name Major Revision # Minor Revision # Description MCS File
SIS38200101 01 01 Initial Release -
SIS38200102 01 02 add mode, 512 MB SDRAM support, VME firmware upgrade  
SIS38200103 01 03 CBLT implementation  
SIS38200104 01 04 48-bit deep channels 1 and 17  
SIS38200105 01 05 new control out mode 2, 10 MHz  
SIS38200106 01 06 FIFO mode bug fix of 01 05 (wrap beyond 64MB)  
SIS38200107 01 07 bug fix of 01 06 (partial readout)  
SIS38200108 01 08 new input control mode with external clear sis38200108.mcs
SIS38200109 01 09 inhibit veto registerbug fix output inversion sis38200109.mcs
SIS3820010A 01 0A test pulse mask register sis3820010A.mcs
SIS3820010B 01 0B OUT MUX functionality  
SIS3820010C 01 0C modified version of B, add register reset with VME Sysreset sis3820010C.mcs
SIS3820010D 01 0D Encoder readout feature added sis3820010D.mcs
SIS3820010E 01 0E support for new 512 MB memory strip added use 0x0110
SIS3820010F 01 0F early LNE with channel N LNE bug fix, new 512 MB missing use 0x0110
SIS38200110 01 10 early LNE with channel N LNE bug fix and new 512 MB strip sis38200110.mcs
SIS38200111 01 11 New CIP/LNE Delay/Width and Invert functionality sis38200111.mcs
SIS3820 Multi Purpose Counter
SIS3820 I/O Register/Latches
Design Name Major Revision # Minor Revision # Description MCS File
SIS38200F001 F0 01 16 Input/16 Output Latch with counters sis3820_f001.mcs
SIS38200F101 F1 01 32 Input Register Use F102
SIS38200F102 F1 02 32 Input Register w. bug fix sis3820_f102.mcs
SIS38200F202 F2 02 32 Input Register with TASCA extensions sis3820_f202.mcs
SIS38200F203 F2 03 32 Input Register with TASCA extensions w. 512 MB support sis3820_f203.mcs
SIS38200F301 F3 01 32 Channel Output with IRQ functionality sis3820_f301.mcs
SIS3820 I/O Register/Latches
SIS3820 Clock Distributor
Design Name Major Revision # Minor Revision # Description MCS File
SIS38200E001 E0 01 Clock distributor -
SIS38200E002 E0 02 Clock distributor with input inversion sis3820E002.mcs
SIS38200E003 E0 03 Clock distributor with input inversion and clock doubling 40 and 50 MHz Quarz sis3820E003.mcs
SIS38200E203 E2 03 Clock distributor with input inversion and clock doubling 50 and 100 MHz Quarz Use E204
SIS38200E204 E2 04 Like E203, new 32 start/stop only mode sis3820E204.mcs
SIS38200E205 E2 05 Like E204, programmable start/stop delay sis3820E205.mcs
SIS3820 Clock Distributor
SIS3820 Logic Module
Design Name Major Revision # Minor Revision # Description MCS File
SIS38200E801 E8 01 Vetoed 2 times 8-fold coincidence with fan out sis3820_e801.mcs
SIS3820 Logic Module
SIS3820 Pattern Generator w. I/O
Design Name Major Revision # Minor Revision # Description MCS File
SIS38206001 60 01 APG with I/O sis3820_6001.mcs
SIS3820 Pattern Generator w. I/O for SIS3820 Inline and LVDS configurations

JTAG firmware upgrade procedure

The firmware of the SIS3820 can be ugraded with a XILINX JTAG programmer (XILINX part number HW-USB-II-G-JTAG e.g.) through the serial port of a Windows PC. Download firmware upgrade instruction. Firmware upgrade from the VME bus is supported in the latest revisions of the firmware.