SIS3820 Firmware revision table
| Design Name | Major Revision # | Minor Revision # | Description | MCS File |
|---|---|---|---|---|
| SIS38200101 | 01 | 01 | Initial Release | - |
| SIS38200102 | 01 | 02 | add mode, 512 MB SDRAM support, VME firmware upgrade | |
| SIS38200103 | 01 | 03 | CBLT implementation | |
| SIS38200104 | 01 | 04 | 48-bit deep channels 1 and 17 | |
| SIS38200105 | 01 | 05 | new control out mode 2, 10 MHz | |
| SIS38200106 | 01 | 06 | FIFO mode bug fix of 01 05 (wrap beyond 64MB) | |
| SIS38200107 | 01 | 07 | bug fix of 01 06 (partial readout) | |
| SIS38200108 | 01 | 08 | new input control mode with external clear | sis38200108.mcs |
| SIS38200109 | 01 | 09 | inhibit veto registerbug fix output inversion | sis38200109.mcs |
| SIS3820010A | 01 | 0A | test pulse mask register | sis3820010A.mcs |
| SIS3820010B | 01 | 0B | OUT MUX functionality | |
| SIS3820010C | 01 | 0C | modified version of B, add register reset with VME Sysreset | sis3820010C.mcs |
| SIS3820 Multi Purpose Counter | ||||
| Design Name | Major Revision # | Minor Revision # | Description | MCS File |
|---|---|---|---|---|
| SIS38200F001 | F0 | 01 | 16 Input/16 Output Latch with counters | sis3820_f001.mcs |
| SIS38200F101 | F1 | 01 | 32 Input Register | sis3820_f101.mcs |
| SIS38200F202 | F2 | 02 | 32 Input Register with TASCA extensions | sis3820_f202.mcs |
| SIS3820 I/O Register/Latches | ||||
| Design Name | Major Revision # | Minor Revision # | Description | MCS File |
|---|---|---|---|---|
| SIS38200E001 | E0 | 01 | Clock distributor | - |
| SIS38200E002 | E0 | 02 | Clock distributor with input inversion | sis3820E002.mcs |
| SIS38200E003 | E0 | 03 | Clock distributor with input inversion and clock doubling 40 and 50 MHz Quarz | sis3820E003.mcs |
| SIS38200E203 | E2 | 03 | Clock distributor with input inversion and clock doubling 50 and 100 MHz Quarz | Use E204 |
| SIS38200E204 | E2 | 04 | Like E203, new 32 start/stop only mode | sis3820E204.mcs |
| SIS3820 Clock Distributor | ||||
| Design Name | Major Revision # | Minor Revision # | Description | MCS File |
|---|---|---|---|---|
| SIS38200E801 | E8 | 01 | Vetoed 2 times 8-fold coincidence with fan out | sis3820_e801.mcs |
| SIS3820 Logic Module | ||||
JTAG firmware upgrade procedure
The firmware of the SIS3820 can be ugraded with a XILINX JTAG programmer (XILINX part number HW-USB-II-G-JTAG e.g.) through the serial port of a Windows PC. Download firmware upgrade instruction. Firmware upgrade from the VME bus is supported in the latest revisions of the firmware.
