SIS3316 Firmware Page

SIS3316 125 MSPS Firmware Revision Table
Design Name VME FPGA Revision # ADC FPGA Revision # Description Archive with Files
125 MHz 120614 0x33162005 0x01250006 Peak, Charge, Tap Delay,... version_125MHz_2014-06-12_V33162005_A01250006.zip
125 MHz 151214 0x33162006 0x01250008 Sample Length, DHCP,... version_125MHz_2014-12-15_V33162006_A01250008.zip
*** new UDP protocol ***
125 MHz 270315 0x33162008 0x01250008 Trigger Lookup Table version_125MHz_2015-03-27_V33162008_A01250008.zip
125 MHz 040615 0x33162009 0x01250009 2 and 4 G memory chip init (units above SN 201 have 4G) version_125MHz_2015-06-04_V33162009_A01250009.zip
125 MHz 290715 0x3316200A 0x0125000A Optical Ethernet Support version_125MHz_2015-07-29_V3316200A_A0125000A.zip
125 MHz 160316 0x3316200B 0x0125000B
    bug fix for rare Multievent Bank Swap logic stops
    New External Veto/Gate Delay register
    internal SUM-Trigger stretched pulse ch…to VME FPGA
version_125MHz_2016-03-16_V3316200B_A0125000B.zip
125 MHz 310816 0x3316200B 0x0125000C
    bug fix for long P start condition
version_125MHz_2016-03-16_V3316200B_A0125000C.zip
SIS3316 125 MSPS Firmware Revision Table
SIS3316 250 MSPS Firmware Revision Table
Design Name VME FPGA Revision # ADC FPGA Revision # Description Archive with Files
250 MHz 121109 0x33162001 0x02500001 Initial release obsolete
250 MHz 130124 0x33162002 0x02500002 Ethernet, fixes, dual threshold Version_250MHz_2013-01-24.zip
250 MHz 130211 0x33162002 0x02500003 2 bug fixes. ADC SPI read (Bit 0 was 1 always), actual/previous address counter read (w. update mode bit in trigger statistics counter mode register set) Version_250MHz_2013-02-11.zip
250 MHz 130411 0x33162003 0x02500003 fully licensed Ethernet core, external bank switch, bug fixes Version_250MHz_2013-04-11.zip
250 MHz 131127 0x33162004 0x02500004 Energy filter and histogram, stretched trigger, ... Version_250MHz_2013-11-27.zip
250 MHz 120614 0x33162005 0x02500006 Peak, Charge, Tap Delay,... version_250MHz_2014-06-12_V33162005_A02500006.zip
250 MHz 151214 0x33162006 0x02500008 Sample Length, DHCP,... use version below
250 MHz 161214 0x33162006 0x02500008 Timing issue fixed version_250MHz_2014-12-16_V33162006_A02500008.zip
*** new UDP protocol ***
250 MHz 270315 0x33162008 0x02500008 Trigger Lookup Table version_250MHz_2015-03-27_V33162008_A02500008.zip
250 MHz 040615 0x33162009 0x02500009 2 and 4 G memory chip init (units above SN 176 have 4G) version_250MHz_2015-06-04_V33162009_A02500009.zip
250 MHz 290715 0x3316200A 0x0250000A Optical Ethernet Support version_250MHz_2015-07-29_V3316200A_A0250000A.zip
250 MHz 160316 0x3316200B 0x0250000B
    bug fix for rare Multievent Bank Swap logic stops
    New External Veto/Gate Delay register
    internal SUM-Trigger stretched pulse ch…to VME FPGA
version_250MHz_2016-03-16_V3316200B_A0250000B.zip
SIS3316 250 MSPS Firmware Revision Table

JTAG firmware upgrade procedure

The firmware of the SIS3316 can be ugraded with a XILINX JTAG USB programmer from a Windows PC (XILINX part number HW-USB-II-G-JTAG, Struck part number 02950). Firmware upgrade over VME and Ethernet is supported also.