SIS1100(e)/SIS3100 firmware page

SIS1100/3100 Firmware Revision Table
Design/MCS files SIS1100 Major SIS1100 Minor SIS3100 Major SIS3100 Minor Description
V_120701         SIS3100 Standard Design
V_310502 1 6 1 4 SIS3100 Standard Design
V_160802 1 6 1 5 VME interrupt generation added
no other changes
V_051202 1 7 1 5 rare XOFF problem with block transfer
V_120903 (up to 13.4.04 wrong SIS1100 file in archive, fixed) 1 7 1 6 DSP/PC SDRAM/optical arbitration fix
D32 access with address bit 2 set after MBLT64
V_070307 1 7 1 7 SIS3100 FIFO for XOFF during BLT added
SIS1100/3100 Firmware Revision Table

SIS1100/3100 firmware upgrade manual version 1.40

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SIS1100e PEX8311 EEPROM File

Prefetchable base address capability has to be enabled on the PEX8311 PCI Express to local bus bridge chip to perform 64-bit direct master or DMA transfers. This is of relevance on machines from 4 GB of memory on. The corresponding bits can be set through the configuration EEPROM of the PEX8311. Units with serial number 94 and higher are shipped with this configuration. The EEPROM can be regrogrammed with the PLX Technology SDK. The V2 EEPROM file can be found here. vertical bar