

CORE Generator Options:
   Target Device                 : xc6vlx130t-ff1156
   Speed Grade                   : -2
   HDL                           : vhdl
   Synthesis Tool                : Foundation_ISE

MIG Output Options:
   Module Name                   : ddr3_ram
   No of Controllers             : 1
   Selected Compatible Device(s) : --
   Hardware Test Bench           : disabled

FPGA Options:
   Clock Type                    : Single-Ended
   Debug Port                    : OFF
   Internal Vref                 : disabled

Extended FPGA Options:
   DCI for DQ, DQS/DQS#          : enabled
   DCI for Address/Control       : disabled
    
/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                 : DDR3_SDRAM
   Interface              : NATIVE
   Design Clock Frequency : 2500 ps (400.00 MHz)
   Memory Type            : Components
   Memory Part            : MEM-4G-256Mx16
   Equivalent Part(s)     : --
   Data Width             : 64
   ECC                    : Disabled
   Data Mask              : enabled
   ORDERING               : Strict

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 6
   Output Drive Strength (MR1[5,1]) : RZQ/7
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/4
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off

Selected Banks and Pins usage : 
       Data          :bank 12(40) -> Number of pins used : 24 
                      bank 22(40) -> Number of pins used : 24 
                      bank 23(40) -> Number of pins used : 24 
                      bank 32(40) -> Number of pins used : 24 
                      
       Address/Control:bank 33(40) -> Number of pins used : 28 
                      
       System Clock  :bank 24(40) -> Number of pins used : 2 
                      
       
       VRN/VRP       :bank 12(40) -> Number of pins used : 2 
                      bank 22(40) -> Number of pins used : 2 
                      bank 23(40) -> Number of pins used : 2 
                      bank 32(40) -> Number of pins used : 2 
                      
       VREF          :bank 12(40) -> Number of pins used : 2 
                      bank 22(40) -> Number of pins used : 2 
                      bank 23(40) -> Number of pins used : 2 
                      bank 32(40) -> Number of pins used : 2 
                      
       BUFR          :bank 12(40) -> Number of pins used : 1 
                      bank 23(40) -> Number of pins used : 1 
                      bank 33(40) -> Number of pins used : 1 
                      
       BUFIO         :bank 12(40) -> Number of pins used : 2 
                      bank 22(40) -> Number of pins used : 2 
                      bank 23(40) -> Number of pins used : 2 
                      bank 32(40) -> Number of pins used : 2 
                      
       Total IOs used :    145



Notes:

   1) IODELAY Power Versus Performance option (FPGA Options page) is removed
      from selection and is always set to HIGH internally from 3.8 release.
      IODELAY_HP_MODE parameter value will be always "ON" in
      MIG generated RTL.

   2) RTT (nominal) - On Die Termination (ODT) selection value of "Disabled" is
      removed from selection and one of the RTT values (RZQ/4, RZQ/2 and RZQ/6)
      should be selected. In Verify UCF and Update Design flow, MIG will set
      RTT_NOM parameter as 60 (i.e., RZQ/4) in MIG generated RTL for
      RTT value of "Disabled".
    