                                                          Log file                                                       

Generated by MIG MIG Version 3.92Build NumberP.49d on Mi 27. Feb 14:17:45 2013


Reading design libraries of xc6vlx130t-ff1156... successful !
Creating the temp directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_designCreating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design...successful.
...successful!
Creating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/par...successful!
Creating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/docs ...successful! 
Creating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/synth ...successful! 
Creating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/sim ...successful! 
Creating the directory D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl ...successful! 
Creating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/par/example_top.ucf...successful!
Writing the headers to D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/par/example_top.ucf  ...successful!

/*******************************************************/
/*                    Controller 0                                                 
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Mask bits ...
Checking pins allocated to Clock bits ... 
Checking pins allocated to Control bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
Allocating pins for memory clock signals ...successful!
Allocating pins for memory clock signals ...successful!
Allocating pins for address signals ...successful!
Allocating pins for bank address signals ...successful!
Allocating pins for memory control signals ...successful!
Allocating pins for data signals, strobes, data masks and Read Enables  ...successful!
Allocating pins to System Control signals  ...successful!
Allocating pins to system clock signals  ...successful!
Writing the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram_signalinfo_0.xml ...successful!
Copying all the files from docs ...
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/arb_mux.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/arb_row_col.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/arb_select.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_cntrl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_common.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_compare.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_mach.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_queue.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/bank_state.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/col_mach.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/mc.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/rank_cntrl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/rank_common.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/rank_mach.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/controller/round_robin_arb.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ecc/ecc_buf.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ecc/ecc_dec_fix.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ecc/ecc_gen.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ecc/ecc_merge_enc.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/ddr2_ddr3_chipscope.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/clk_ibuf.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/iodelay_ctrl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/infrastructure.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/mem_intfc.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/memc_ui_top.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/circ_buffer.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_ck_iob.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_clock_io.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_control_io.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_data_io.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_dly_ctrl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_dm_iob.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_dq_iob.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_dqs_iob.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_init.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_pd_top.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_pd.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_rdclk_gen.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_rdctrl_sync.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_rddata_sync.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_rdlvl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_read.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_top.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_write.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/phy_wrlvl.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/phy/rd_bitslip.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ui/ui_cmd.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ui/ui_rd_data.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ui/ui_top.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ui/ui_wr_data.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/sim/ddr3_model_parameters.vh ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/sim/ddr3_model.v ...successful!
 ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ddr3_ram_ucf_constraints_0.vhd ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/synth/ddr3_ram_dcm_constraints.sdc ...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/sim/sim_tb_top.vhd ...successful!

Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/par/example_top.ucf ...successful!
...successful!
Generating the file D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl/ip_top/example_top.vhd......successful! 


Result:
        Successful!
The design output files are located in D:/work/8300-L/xilinx/sis8300l/ipcore_dir/tmp/_cg/ddr3_ram/example_design/rtl and ..example_design/par for rtl & ucf files respectively.