# Output products list for <dual_ram2kx18>
_xmsgs\pn_parser.xmsgs
dual_ram2kx18.asy
dual_ram2kx18.gise
dual_ram2kx18.ngc
dual_ram2kx18.sym
dual_ram2kx18.vhd
dual_ram2kx18.vho
dual_ram2kx18.xco
dual_ram2kx18.xise
dual_ram2kx18\blk_mem_gen_v7_3_readme.txt
dual_ram2kx18\doc\blk_mem_gen_v7_3_vinfo.html
dual_ram2kx18\doc\pg058-blk-mem-gen.pdf
dual_ram2kx18\example_design\dual_ram2kx18_exdes.ucf
dual_ram2kx18\example_design\dual_ram2kx18_exdes.vhd
dual_ram2kx18\example_design\dual_ram2kx18_exdes.xdc
dual_ram2kx18\example_design\dual_ram2kx18_prod.vhd
dual_ram2kx18\implement\implement.bat
dual_ram2kx18\implement\implement.sh
dual_ram2kx18\implement\planAhead_ise.bat
dual_ram2kx18\implement\planAhead_ise.sh
dual_ram2kx18\implement\planAhead_ise.tcl
dual_ram2kx18\implement\xst.prj
dual_ram2kx18\implement\xst.scr
dual_ram2kx18\simulation\addr_gen.vhd
dual_ram2kx18\simulation\bmg_stim_gen.vhd
dual_ram2kx18\simulation\bmg_tb_pkg.vhd
dual_ram2kx18\simulation\checker.vhd
dual_ram2kx18\simulation\data_gen.vhd
dual_ram2kx18\simulation\dual_ram2kx18_synth.vhd
dual_ram2kx18\simulation\dual_ram2kx18_tb.vhd
dual_ram2kx18\simulation\functional\simcmds.tcl
dual_ram2kx18\simulation\functional\simulate_isim.bat
dual_ram2kx18\simulation\functional\simulate_mti.bat
dual_ram2kx18\simulation\functional\simulate_mti.do
dual_ram2kx18\simulation\functional\simulate_mti.sh
dual_ram2kx18\simulation\functional\simulate_ncsim.sh
dual_ram2kx18\simulation\functional\simulate_vcs.sh
dual_ram2kx18\simulation\functional\ucli_commands.key
dual_ram2kx18\simulation\functional\vcs_session.tcl
dual_ram2kx18\simulation\functional\wave_mti.do
dual_ram2kx18\simulation\functional\wave_ncsim.sv
dual_ram2kx18\simulation\random.vhd
dual_ram2kx18\simulation\timing\simcmds.tcl
dual_ram2kx18\simulation\timing\simulate_isim.bat
dual_ram2kx18\simulation\timing\simulate_mti.bat
dual_ram2kx18\simulation\timing\simulate_mti.do
dual_ram2kx18\simulation\timing\simulate_mti.sh
dual_ram2kx18\simulation\timing\simulate_ncsim.sh
dual_ram2kx18\simulation\timing\simulate_vcs.sh
dual_ram2kx18\simulation\timing\ucli_commands.key
dual_ram2kx18\simulation\timing\vcs_session.tcl
dual_ram2kx18\simulation\timing\wave_mti.do
dual_ram2kx18\simulation\timing\wave_ncsim.sv
dual_ram2kx18_flist.txt
dual_ram2kx18_xmdf.tcl
summary.log
