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-------------------------------------------------------------------------------
-- Project    : Virtex-6 Integrated Block for PCI Express
-- File       : pci_exp_usrapp_cfg.vhd
-- Version    : 1.7
--
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.test_interface.all;

entity pci_exp_usrapp_cfg is

port (

  cfg_do                   : in std_logic_vector((32 - 1) downto 0);
  cfg_di                   : out std_logic_vector((32 - 1) downto 0);
  cfg_byte_en_n            : out std_logic_vector(((32/8) - 1) downto 0);
  cfg_dwaddr               : out std_logic_vector((10 - 1) downto 0);
  cfg_wr_en_n              : out std_logic;
  cfg_rd_en_n              : out std_logic;
  cfg_rd_wr_done_n         : in std_logic;
  cfg_err_cor_n            : out std_logic;
  cfg_err_ur_n             : out std_logic;
  cfg_err_ecrc_n           : out std_logic;
  cfg_err_cpl_timeout_n    : out std_logic;
  cfg_err_cpl_abort_n      : out std_logic;
  cfg_err_cpl_unexpect_n   : out std_logic;
  cfg_err_posted_n         : out std_logic;
  cfg_err_tlp_cpl_header   : out std_logic_vector(( 48 - 1) downto 0);
  cfg_interrupt_n          : out std_logic;
  cfg_interrupt_rdy_n      : in std_logic;
  cfg_turnoff_ok_n         : out std_logic;
  cfg_to_turnoff_n         : in std_logic;
  cfg_pm_wake_n	           : out std_logic;
  cfg_bus_number           : in std_logic_vector((8 -1) downto 0);
  cfg_device_number        : in std_logic_vector((5 - 1) downto 0);
  cfg_function_number      : in std_logic_vector((3 - 1) downto 0);
  cfg_status               : in std_logic_vector((16 - 1) downto 0);
  cfg_command              : in std_logic_vector((16 - 1) downto 0);
  cfg_dstatus              : in std_logic_vector((16 - 1) downto 0);
  cfg_dcommand             : in std_logic_vector((16 - 1) downto 0);
  cfg_lstatus              : in std_logic_vector((16 - 1) downto 0);
  cfg_lcommand             : in std_logic_vector((16 - 1) downto 0);
  cfg_pcie_link_state_n    : in std_logic_vector((3 - 1) downto 0);
  cfg_trn_pending_n        : out std_logic;

  trn_clk                  : in std_logic;
  trn_reset_n              : in std_logic

);


end pci_exp_usrapp_cfg;

architecture rtl of pci_exp_usrapp_cfg is

begin

  -- Signals not used by testbench at this point
  cfg_err_cor_n <= '1';
  cfg_err_ur_n <= '1';
  cfg_err_ecrc_n <= '1';
  cfg_err_cpl_timeout_n <= '1';
  cfg_err_cpl_abort_n <= '1';
  cfg_err_cpl_unexpect_n <= '1';
  cfg_err_posted_n <= '0';
  cfg_interrupt_n <= '1';
  cfg_turnoff_ok_n <= '1';
  cfg_err_tlp_cpl_header <= (others => '0');
  cfg_pm_wake_n <= '1';
  cfg_trn_pending_n <= '0';

  ------------------
  -- The following signals are driven by processes defined in
  -- test_package and called from tests.vhd
  ------------------

  -- Inputs to CFG procecces / Outputs of core
  cfg_rdwr_int.trn_clk          <= trn_clk;
  cfg_rdwr_int.trn_reset_n      <= trn_reset_n;
  cfg_rdwr_int.cfg_rd_wr_done_n <= cfg_rd_wr_done_n;
  cfg_rdwr_int.cfg_do           <= cfg_do;

  -- Outputs of CFG processes / Inputs to core
  cfg_dwaddr     <= cfg_rdwr_int.cfg_dwaddr;
  cfg_di         <= cfg_rdwr_int.cfg_di;
  cfg_byte_en_n  <= cfg_rdwr_int.cfg_byte_en_n;
  cfg_wr_en_n    <= cfg_rdwr_int.cfg_wr_en_n;
  cfg_rd_en_n    <= cfg_rdwr_int.cfg_rd_en_n;

end;  -- pci_exp_usrapp_cfg
