The SIS3806 is a stripped version of the SIS3801 multiscaler board. It was designed with experiments with a small channel count in mind. The control input section is identical to the SIS3801, the eight counter inputs are fed into the unit via a 34 pin header (ECL and flat cable TTL version) or via 8 LEMO connectors (NIM and LEMO TTL version) in the lower portion of the board.
EPICS support by Mark Rivers http://cars9.uchicago.edu/software/dev_mca_struck.html.
In contrast to Firmware versions 1 - 6, versions 7 and 8 are not dual bank multiscaler implementations, but latching scaler designs. The scaler content is latched to the shadow register upon a VME or an external LNE (load next event) and copied to the FIFO. Up to a maximum count rate of 1 MHz no count will be lost in this process. The scalers are not cleared upon readout, clear has to be issued via VME or the two clear front panel inputs.
1 MHz maximum count rate (no missing count on read on the fly)
Individual external clear for even and odd channels
CBLT style readout
Event time stamping with down to 1 µs resolution
moderate count rate/no clear multiscaling