SIS3700 32-bit ECL input FIFO


The SIS3700 is a receiver board for ECL or LVDS data streams with a width of up to 32-bits. The card is optimised for the acquisition of FERA and PCOS data streams. Various end conditions, like timeout e.g., are implemented. Data can be read out through VME or a P2 row A/C cable bus in parallel to the acquisition of new data, as decoupling is handled by the on board FIFO chips.


Features/Properties:

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32-bit ECL input (LVDS option available)

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40 MB/s input rate

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Event structure

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Different end of event conditions

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1K deep event and data FIFO (4K/16K/64K available on request)

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16-bit pack mode

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VME access, user LED and 4 status LEDs

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A24/A32/D32/BLT32 slave interface

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P2 A/C local bus readout capability

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VME FIFO test capability

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VME64x Connectors

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VME64x Side Shielding

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Single +5V supply


Simplified block diagram:

SIS3700 block diagram

Picture of SIS3700

SIS3700 photograph

Application examples:

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PCOS/FERA readout (dual ported memory replacement)

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Serialized pixel/strip detector readout


Last update 30.08.01 by Matthias Kirsch