ADSP-21060/62 SHARC DSP Chip
The Analog Devices 21060/62 Super Harvard Architecture Computer (SHARC) is a
high performance 32-bit digital signal processor for speech, sound, graphics
and imaging applications. Its architecture makes it perfectly suited for data
acquisition in physics and other fields. The chip builds on the ADSP-21000
family DSP core to form a complete system on one chip by adding dual-ported on
chip SRAM and integrated I/O peripherals by a dedicated I/O bus. With its
on-chip instruction cache, the processor can execute every instruction in a
single cycle. Four independent buses for dual data, instructions, and I/O, plus
crossbar switch memory connections comprise the Super Harvard Architecture of
the ADSP-2106x.
Architectural features:
- 32-Bit IEEE Floating-Point Computation Units-multiplier, ALU, and Shifter
- Data Register File
- Data Address Generators (DAG1, DAG2)
- Program Sequencer with Instruction Cache
- Interval Timer
- Dual-Ported SRAM
- External Port for Interfacing to Off-Chip Memory & Peripherals
- Host Port & Multiprocessor Interface
- DMA Controller
- Serial Ports
- Link Ports
- JTAG Test Access Port
Technical Characteristics:
- 40 MIPS, 25 ns instruction cycle at 40 MHz
- 120 MFLOPS peak, 80 MFLOPS sustained at 40 MHz
- Data formats:
- IEEE standard 754/854 32 Bit floating point format
- IEEE Extended 40 Bit floating point format
- 32 Bit fixed point, integer & fractional with 80-Bit accumulators
- On-Chip memory
- 4 MBit (ADSP-21060)
- 2 MBit (ADSP-21062)
- Dual ported to core processor and DMA
- Usable as program and data memory
- Off-Chip memory
- 4 Gigabyte address space (32 Bit address)
- 48 Bit bus for program and data memory
- DMA controller
- 10 DMA channels
- Background DMA transfer at 40 MHz in parallel to full speed processor
execution
- Background transfers in between of ADSP-2106x internal and external memory,
external peripherals, host processor, serial ports or link ports
- Multiprocessing
- Six ports for point-to-point connectivity and array multiprocessing
- 240 MByte/s transfer rate over parallel bus
- 240 MByte/s over link ports
- Serial ports
- Two 40 MBit/s synchronous serial ports
- Independent transmit & receive functions
- 3- to 32-Bit data word width
- µ-Law/A-Law hardware companding
- TDM multichannel mode
Last update: 9.4.98 by Matthias Kirsch